The present disclosure relates to integrated circuits (IC), and more specifically, to a gated differential logic circuit having a pair of miller connected capacitors configured to reduce power consumption and jitter.
Integrated circuits (ICs) used in digital electronic systems such as microprocessors, computer memory, and digital imaging sensors can be constructed from complementary metal oxide semiconductor (CMOS) devices. CMOS devices can include complementary and symmetrical networks of N-type and P-type metal oxide semiconductor field effect transistors (MOSFETs). In some CMOS devices, a network of N-type MOSFETs (NMOS) transistors can drive logic signals low (e.g., pull-down a logic signal to the negative end of a supply rail, such as ground), while a network of P-type MOSFETs (PMOS) may drive logic signals high (e.g., pull-up a logic signal to supply a voltage, such as VCC).
CMOS devices, such as clock buffers, can be driven by, and produce, differential signals where both true and complement signals are provided for a given logic function. These CMOS differential devices can include pairs of mirrored driver circuits, with each circuit operating on, and producing, one signal of a differential pair. In some systems, the driver circuits can be constructed on top of each other using stacked or cascaded CMOS devices.
Power consumption and jitter are influenced by the number of interconnected circuits in an IC. Switching power consumption includes a measure of the amount of energy dissipated by CMOS circuits as they transition from one binary state to another and can increase for the overall IC with the number of interconnected circuits. Jitter is a measure of a clock signal's deviation from its designed period. Jitter, like power consumption, can increase with the number of interconnected CMOS circuits in an IC.